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  ? semiconductor components industries, llc, 2001 march, 2001 rev. 3 1 publication order number: mtp8n50e/d tmos e-fet . ? power field effect transistor nchannel enhancementmode silicon gate this high voltage mosfet uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over time. in addition, this advanced tmos efet is designed to withstand high energy in the avalanche and commutation modes. this new energy efficient design also offers a draintosource diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, converters, pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? robust high voltage termination ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 500 vdc draintogate voltage (r gs = 1.0 m  ) v dgr 500 vdc gatetosource voltage continuous gatetosource voltage nonrepetitive (tp 10 ms) v gs v gsm 20 40 vdc vpk drain current e continuous @ t c = 25 c drain current e continuous @ t c = 100 c drain current e single pulse (tp 10  s) i d i d i dm 8.0 5.0 32 adc apk total power dissipation @ t c = 25 c derate above 25 c p d 125 1.0 watts w/ c operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, peak i l = 8.0 apk, l = 16 mh, r g = 25  ) e as 510 mj thermal resistance junctiontocase junctiontoambient r  jc r  ja 1.0 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 5 sec. t l 260 c mtp8n50e tmos power fet 8.0 amperes 500 volts r ds(on) = 0.8 ohm d s g case 221a09, style 5 to-220ab
mtp8n50e http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 500 e e 500 e e vdc mv/ c zero gate voltage drain current (v ds = 500 vdc, v gs = 0 vdc) (v ds = 400 vdc, v gs = 0 vdc, t j = 125 c) i dss e e e e 250 1000  adc gatebody leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss e e 100 nadc on characteristics (1) gate threshold voltage (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 2.0 e 2.8 6.3 4.0 e vdc mv/ c static draintosource onresistance (v gs = 10 vdc, i d = 4.0 adc) r ds(on) e 0.6 0.8 ohms draintosource onvoltage (v gs = 10 vdc) (i d = 8.0 adc) (i d = 4.0 adc, t j = 125 c) v ds(on) e e 5.0 e 7.2 6.4 vdc forward transconductance (v ds = 15 vdc, i d = 4.0 adc) g fs 4.0 e e mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss e 1450 1680 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss e 190 246 transfer capacitance f = 1 . 0 mhz) c rss e 45.4 144 switching characteristics (2) turnon delay time t d(on) e 15 50 ns rise time (r + c17n 9 1  ) t r e 33 72 turnoff delay time (r go + c17n = 9.1  ) t d(off) e 40 150 fall time t f e 32 60 gate charge (fi 8) q t e 40 64 nc (see figure 8) (v ds = 400 vdc, i d = 8.0 adc, q 1 e 8.0 e (v ds 400 vdc , i d 8 . 0 adc , v gs = 10 vdc) q 2 e 17 e q 3 e 17.3 e sourcedrain diode characteristics forward onvoltage v sd vdc forward on voltage (i s = 8.0 adc, v gs = 0 vdc) (i 80ad v 0vd t 125 c) v sd e 1.2 2.0 vdc s gs (i s = 8.0 adc, v gs = 0 vdc, t j = 125 c) e 1.1 e reverse recovery time t rr e 320 e ns (i s = 8.0 adc, v gs = 0 vdc, t a e 179 e (i s 8 . 0 adc , v gs 0 vdc , di s /dt = 100 a/  s) t b e 141 e reverse recovery stored charge q rr e 3.0 e  c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d e 4.5 e nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s e 7.5 e (1) pulse test: pulse width 300  s, duty cycle 2.0%. (2) switching characteristics are independent of operating junction temperature.
mtp8n50e http://onsemi.com 3 typical electrical characteristics 100 c 25 c t j = -55 c v ds , drain-to-source voltage (volts) figure 1. onregion characteristics v gs , gate-to-source voltage (volts) figure 2. transfer characteristics i d , drain current (amps) figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. draintosource leakage current versus voltage r ds(on) , drain-to-source resistance (normalized) i dss , leakage (na) r ds(on) , drain-to-source resistance (ohms) 16 12 8.0 4.0 10 8.0 6.0 4.0 2.0 0 16 12 8.0 4.0 2.0 2.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.8 0.6 0.4 0.2 0 14 10 6.0 2.0 0 0.60 0 4.0 8.0 12 16 2.5 1.5 0.5 0 150 100 50 0 -50 t j = 25 c 7 v 6 v 5 v i d , drain current (amps) v gs = 10 v 0 4.0 8.0 12 16 2.0 6.0 10 14 0 100 300 500 200 400 0 2.0 1.0 100,000 1,000 10 1.0 10,000 100 14 12 8 v i d , drain current (amps) 0.55 0.70 0.65 0.75 0.85 0.80 t j = 25 c v gs = 10 v 15 v 1.6 1.2 1.0 r ds(on) , drain-to-source resistance (ohms) v gs = 10 v t j = 100 c 25 c -55 c 125 75 25 -25 v gs = 10 v i d = 8 a v gs = 0 v t j = 125 c 25 c 100 c v ds 10 v 3.0 3.5 14 10 6.0 2.0 1.4 0.90
mtp8n50e http://onsemi.com 4 typical electrical characteristics gate-to-source or drain-to-source voltage (volts) figure 7. capacitance variation drain-to-source voltage (volts) figure 8. high voltage capacitance variation q g , total gate charge (nc) figure 9. gatetosource and draintosource voltage versus total charge r g , gate resistance (ohms) figure 10. resistive switching time variation versus gate resistance v sd , source-to-drain voltage (volts) figure 11. diode forward voltage versus current v ds , drain-to-source voltage (volts) figure 12. maximum rated forward biased safe operating area i s , source current (amps) i d , drain current (amps) v c, capacitance (pf) t, time (ns) 4000 3000 2000 1000 20 10 5.0 0 -5.0 -10 10,000 1,000 100 10 100 1000 8.0 6.0 4.0 2.0 0 32 24 16 8.0 0 1000 100 10 1.0 10 100 6.0 2.0 0 0.9 0.8 0.7 0.6 0.5 c, capacitance (pf) 10 40 0.1 1.0 10 100 1000 0 8.0 4.0 100 10 0.1 0.01 1.0 15 25 12 10 , gate-to-source voltage (volts) gs 1.3 1.2 1.1 1.0 t j = 25 c v gs = 0 v r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c 100  s dc 10 ms 1 ms 10  s t j = 25 c i d = 8 a v dd = 250 v v gs = 10 v t d(off) t r t d(on) v gs = 0 v t j = 25 c c iss c oss c rss v ds = 0 v v gs = 0 v c iss c iss c rss c rss c oss t j = 25 c v gs v ds 400 300 200 100 0 v ds , drain-to-source voltage (volts) t j = 25 c i d = 8 a v ds v gs q2 q1 qt q3 t f
mtp8n50e http://onsemi.com 5 figure 13. maximum avalanche energy versus starting junction temperature e t j , starting junction temperature ( c) 150 25 600 0 100 200 50 100 75 125 300 400 500 i d = 8 a , single pulse drain-to-source as avalanche energy (mj) figure 14. thermal response r(t), normalized effective transient thermal resistance t, time (seconds) 1.0 0.01 d = 0.5 0.05 0.01 single pulse 0.00001 0.02 0.1 0.0001 0.001 0.01 1.0 10 0.1 0.2 0.1
mtp8n50e http://onsemi.com 6 package dimensions case 221a09 issue aa notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. style 5: pin 1. gate 2. drain 3. source 4. drain dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane t c s t u r j
mtp8n50e http://onsemi.com 7 notes
mtp8n50e http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mtp8n50e/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland efet and tmos are trademarks of semiconductor components industries, llc (scillc).


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